1. Field of the Invention
The present invention relates in general to output buffer circuits for integrated circuits, and more particularly to an output buffer circuit for an integrated circuit in which an amount of maximum instantaneous current is reduced and an access time is thus enhanced.
2. Description of the Prior Art
Generally, output buffer circuits act to transfer signals in integrated circuits to other circuits in the outside of the integrated circuits. The output buffer circuits are generally used in semi-conductor memory devices such as a dynamic random access memory (DRAM), a static random access memory (SRAM), a mask read only memory (ROM) and etc. Such an output buffer circuit is shown in FIG. 1, herein.
Referring to FIG. 1, there is shown a circuit diagram of a conventional output buffer circuit. As shown in this drawing, a control signal .PHI.1 is used to control an output signal of the output buffer circuit. Also, two input signals S1 and S2 of the opposite phases are applied to the output buffer circuit.
In the case where the control signal .PHI.1 is "high", the input signal S1 is full-swung to a power source voltage level Vcc through a NAND gate ND1 and an inverter G1. Also, the input signal S2 is full-swung to the power source voltage level Vcc through a NAND gate ND2 and an inverter G2. As a result, a transistor Q1 is turned on/off by the input signal S1 and a transistor Q1' is turned on/off by the input signal S2.
On the contrary, if the control signal .PHI.1 is "low", the input signals S1 and S2 are not applied respectively to the transistors Q1 and Q1', resulting in having no effect on the output signal of the output buffer circuit. In this case, the output signal of the output buffer circuit remains at its state just before the control signal .PHI.1 goes low.
However, the conventional output buffer circuit has a disadvantage in that a large amount of maximum instantaneous current flows upon phase-inversion of the output signal, resulting in generation of a noise. The generation of the noise results in a delay in a data access time. As a result, a circuit performance is degraded.